Aman Chadha • Resume

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Resume

Work Experience

• Google DeepMind: Senior Staff Tech Lead / Senior Manager, Gemini (2026 to Present)

  • Post-training (Agentic Reinforcement Learning, Supervised Fine-tuning, and Evals) for Gemini, aimed at unprecedented use-cases.
  • Managed a team of GenAI engineers and scientists.

• Apple: Senior Manager / Tech Lead, Generative AI (2025 to 2026)

  • Post-training for Apple Intelligence GenAI models, aimed at Apple's ecosystem of devices.
  • Responsibilities span the entire LLM/VLM development lifecycle from data sourcing/filtering to synthetic data generation to fine-tuning and evaluating models.
  • Managed a team of GenAI engineers and managers.

• Amazon Web Services: GenAI Leadership (2023 to 2025)

  • Led a team responsible for NLP, Vision, and Speech models for AWS Customers via the Generative AI Innovation Center.
  • Managed a team of GenAI applied scientists, data scientists, and manager

• Amazon Alexa: AI/ML Leadership (2022 to 2023)

  • Led a team of AI scientists to find innovative ways to advance the field of Speaker Understanding and Personalization.
  • Built AI/ML pipelines that power accurate, on-device features at scale on Amazon Alexa devices.

• Apple AI: Machine Intelligence Neural Design (MIND) Leadership (2018 to 2022)

  • Design machine learning models for a wide range of AI applications including computer vision, NLP, speech recognition.
  • Propose novel ML architectures and methods that achieve state-of-the-art accuracy.
  • Design and train power-efficient ML model for the purpose of deployment on device.
  • Collaborate with other engineers to enable Apple products with efficient and accurate ML solutions.

• Apple: System Performance and Architecture (2016 to 2018)

  • Proven track record in leading the team and architecting new tools/methodologies.
  • Architect Apple's portable and desktop offerings with a focus on performance.
  • Develop projection models to estimate performance of our products, years in advance.
  • Evaluate the performance of next-generation hardware and operating systems.
  • Collaborate with cross-functional teams to debug performance bottlenecks and identify architectural improvement areas.
  • Characterize performance to influence product road-map and make effective power-performance trade-offs.
  • Present performance data and analysis to cross-functional teams including senior management.
  • Identify gaps in test coverage and define new performance tests or bolster existing ones.
  • Drive automation improvements from setup to execution to reporting.

• Qualcomm: ML Subsystem Validation (2014 to 2016)

  • Led the validation of the neural processing subsystem for the Qualcomm AI Engine.
  • Developed drivers for SoC blocks such as the cache coherency module and the memory management unit.
  • Drafted Post-Silicon validation test plans, code test cases in C, perform Emulation and Post-Silicon validation, and debug failures using Trace32.
  • Triaged bugs by identifying sensitivity to process/voltage/temperature and uncovering design/manufacturing/documentation issues. File tickets for the identified issues.
  • Drove several critical hardware debugs from start to completion.
  • Brainstormed and developed a test framework that carried out cache coherency stress-testing which helped identify several hardware bugs, saving $2M in chip respins.
  • Mentored an intern and a new engineer in the team.

• Qualcomm: Pre-Silicon Design Verification (2015)

  • Performed Pre-Silicon Design verification for the SoC's cryptographic core using SystemVerilog and UVM.
  • Drafted Pre-Silicon test plans to identify common and corner use-cases for the core, and code test cases with a focus on functional coverage.
  • Debugged failures using Verdi.

• NVIDIA: GPU Power Team Intern (2013 to 2014)

  • Developed features for an in-house power estimation tool in Python to estimate power and performance numbers for future chips on the company's roadmap.
  • Profiled the tool to identify bottlenecks and optimized the processor-intensive code sections to quicken up the response time.
  • Developed a Python/Bash script that run nightly regressions, parsed and tabulated results as an HTML report, flagged anomalies in the regression runs and sent a report as a daily email.

• Qualcomm: RTL Design Intern (2013)

  • Designed several internal blocks of a new camera-filter IP core in Verilog RTL.
  • Performed RTL linting using Atrenta SpyGlass.
  • Wrote test-benches with randomized control and data signals to verify design functionality.
  • Developed shell scripts to automate routine tasks.

• Research Assistant (2013)

  • FPGA-based hardware development using Verilog for the Compact Muon Solenoid (CMS) experiment for the Large Hadron Collider (LHC) at CERN.

• Project Assistant (2013)

  • Developed web content for the Division of Continuing Studies at UW-Madison.

• Teaching Assistant (2012)

  • TA for the Microprocessors Theory and Lab courses. Dealt with theoretical concepts, programming and problem-solving for ARM7 as well as ARM Cortex M3.

• Research Associate (2011 to 2012)

  • Investigated topics under the domain of biometrics including Face Detection & Recognition, Signature Verification, Voice Recognition and Security of Biometric Templates. Published research results at various international venues.

• Research Staff (2011 to 2012)

  • Development of a research project titled 'Portable Patient Monitoring System'.

• Teaching Assistant (2011)

  • Conducted lab-sessions on Microprocessor and C/C++ Programming.
  • Conducted Image Processing workshops to aid practical understanding of subjects.